Results of the decoupled simulation are verified against the monolithic solution running on a single FPGA platform, logged in Real-Time on #tektronix oscilloscope using a #texasinstruments DAC and post-processed in #MATLAB to remove the noise generated by the measurement system. The plant model implemented in C++14 ( #cpp) is composed of two Dual Active Bridges ( #dabs ) controlled converters– with an execution time step of 35ns. Then it is provided an application example where the parallel bus is employed for #testing and #simulation of #powerelectronics and #powerdistribution #powersystems at system-level employing a fixed small time-step (70ns) typical of device level simulations. The operation of the interface is verified monitoring with ILA and #jtag protocol the data traffic generated with a linear feedback shift register to compare numerical values exchanged over the bus.
In this paper we introduced a low latency parallel bus communication interface for high-speed multi - #FPGA #realtime and hardware-in-the-loop #simulations targeting #xilinx Ultrascale-plus #fpgas and a Virtex-7 #FPGA.
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